1. Field of the Invention
The present invention is related to a method for operating flash memories, and particularly to a method for operating two flash memories on a bus.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a timing diagram illustrating a ready/busy signal R/B, a read enabling signal RE, and a chip enabling signal CE when a host reads a flash memory. As shown in FIG. 1, when a read command of the flash memory is enabled, the ready/busy signal R/B enters a busy waiting time T2. The host starts to toggle the read enabling signal RE when the busy waiting time T2 is over. The host reads data of the flash memory according to a data storing address included by the read command once each time the read enabling signal RE is toggled. When the host starts to toggle the read enabling signal RE, a chip enabling signal CE of the flash memory is changed from high to low. In addition, in an operation specification of a flash memory, a time interval T3 of reading data is longer than the busy waiting time T2, and the busy waiting time T2 is longer than a time interval T1 of the read command.
Please refer to FIG. 2. FIG. 2 is a timing diagram illustrating the host utilizing a time interval of the busy waiting time to read two flash memories simultaneously according to the prior art. As shown in FIG. 2, when a read command A corresponding to a first flash memory on a bus ends, a ready/busy signal ch0AR/B corresponding to the first flash memory enters a busy waiting time BWT1, so that the host can utilize a time interval of the busy waiting time BWT1 to enable a read command B corresponding to a second flash memory. When the busy waiting time BWT1 ends, the host starts to read data F1Data stored in the first flash memory. When the host finishes reading the data F1Data stored in the first flash memory, a time interval of a busy waiting time BWT2 corresponding to the second flash memory also ends, so that the host can immediately start reading data F2Data stored in the second flash memory. The host can enable the read command A of the first flash memory again upon completion of reading the data F2Data stored in the second flash memory. Thus, the host can operate two flash memories on a bus by repeating the above mentioned steps.
However, as shown in FIG. 2, data transmitted on the bus are not compact; that is to say, the bus has some idle time. Therefore, operation efficiency of the prior art does not achieve the best efficiency for operating two flash memories on a bus.